The present invention relates to programmable logic integrated devices (PLDs), and more specifically to techniques and circuitry for implementing vertical line segmentation in a manner that does not conflict with the use of redundancy circuitry.
PLDs have become ubiquitous over the last several years, and are now used in equipment in every major electronics market including telecommunications, data communications, computer peripheral, and industrial, to name just a few. They are a key component in specialized systems in the area of biotechnology, video, automotive, personal computers, and network switches and routers. As the use of PLDs has increased, competition in the marketplace has become fierce, and the price that PLDs command continues to decrease. To improve and maintain profit margins in such an environment, manufactures seek to reduce every element that contributes to the cost of their products.
One key element is the cost of the integrated circuit die. Cost variables include die size and yield. A smaller die results in more total, or gross die on each wafer manufactured. A higher yield means less of the gross die need to be discarded, and more can be sold.
A relatively large portion of a PLD""s die area is allocated to routing resources such as programmable interconnect. If one logic element is connected to another, at least one routing line, or trace is used. If the trace is longer than required, the extra trace length results in wasted die area. When this happens, the die cost is increased unnecessarily. One way to shorten these traces is to segment them into separate line portions. This allows one line to carry more than one signal, since each segmented portion can connect different logic elements together.
Redundancy circuitry is used in integrated circuits to improve the manufacturing yield of good dies. When an integrated circuit has a particular circuit that does not function correctly, the integrated circuit is discarded. But if redundancy circuitry is included on-chip, it can replace the nonfunctioning circuitry. In this way, the integrated circuit is made to function properly and can be sold.
Therefore, it is desirable to provide for line segmentation on PLDs in a manner consistent with the use of redundancy circuitry, such that die size may be minimized while allowing yield improvement.
Accordingly, various embodiments of the present invention provide main and stitch buffers along with a redundant row of logic array blocks. The main buffers, also referred to as segmentation buffers, provide assistance in driving long lines, and can be configured as drivers capable of sending signals either direction along a trace. The main buffers can further be configured as open circuits, such that the segmented portions of a line can carry separate and distinct signals. The redundant row takes the place of a defective row in the PLD. The replacement occurs as the functionality of each row, beginning with the defective one, is moved one row towards the redundant position.
But this shifting requires the alteration of the main buffer""s configuration in some instances. This alteration depends on the main buffer""s initial state, the location of the defective row, as well as the location of the circuitry driving signals on the line. A stitch buffer is added to preserve line segmentation in those circumstances where the main buffer changes from an open circuit to a driver.
It is very desirable to not have to change the programming of a PLD to compensate for the existence of location of a defective row. That is, each device, whether it has a defective row or not, should look the same to a user. Accordingly, an embodiment of the present invention provides for storing data on-chip regarding the location of circuits driving vertical lines, as well as the instructions which tell a row whether to shift for redundancy purposes. This stored data is then used to modify the PLD programming on-chip, resulting in alterations to the instructions provided to the main and stitch buffers.
One exemplary embodiment of the present invention provides a programmable logic device including a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.
The embodiment may further include a second plurality of logic array blocks, wherein the second plurality of logic array blocks are redundant, and are used to replace at least some of the first plurality of logic array blocks when one of the first plurality of logic array blocks are defective.
A further exemplary embodiment of the present invention provides a programmable logic device including a first plurality of logic array blocks arranged contiguously plurality of segmentation buffers arranged contiguously and along a side of the first plurality of logic array blocks, a second plurality of logic array blocks arranged contiguously and along a side of the plurality of segmentation buffers away from the first plurality of logic array blocks, and a plurality of stitch buffers arranged contiguously and along a side of the second plurality of logic array blocks away from the plurality of segmentation buffers. The device also includes a third plurality of logic array blocks arranged contiguously and along a side of the plurality of stitch buffers away from the second plurality of logic array blocks, and a fourth plurality of logic array blocks arranged contiguously and along a side of the third plurality of logic gates away from the plurality of stitch buffers.
Interconnect is also provided, specifically a first plurality of interconnect lines programmably coupled to the first plurality of logic array blocks and coupled to the plurality of segmentation buffers, a second plurality of interconnect lines programmably coupled to the second plurality of logic array blocks, and coupled to the plurality of segmentation buffers and to the plurality of stitch buffers, and a third plurality of interconnect lines programmably coupled to the third plurality of logic array blocks and the fourth plurality of logic array blocks, and coupled to the plurality of stitch buffers. The plurality of segmentation buffers are capable of being configured to drive signals from the first plurality of interconnect lines to the second plurality of interconnect lines, or to drive signals from the second plurality of interconnect lines to the first plurality of interconnect lines, or to provide an open circuit between the first plurality of interconnect lines and the second plurality of interconnect lines.
Yet a further exemplary embodiment of the present invention provides a method of segmenting programmable interconnect lines in a programmable logic device. The device includes a plurality of rows of logic array blocks, a segmentation buffer, and a redundant row of logic array blocks. The method includes determining whether a defective logic array block exists, and if no defective logic array block exists, making no changes to the segmentation buffer, otherwise a location of a defective logic array block is determined. If the location of the defective logic array block is between the segmentation buffer and the redundant row of logic array blocks, then no changes are made to the segmentation buffer, otherwise the location of an active line driver is determined for a line coupled to the segmentation buffer. If the location of the active line driver is in a row of logic blocks next to the segmentation buffer but not between the segmentation buffer and the redundant row of logic blocks, the segmentation buffer is set to drive signals from logic array blocks between the segmentation buffer and the redundant row to logic array blocks not between the segmentation buffer and the redundant row, otherwise the segmentation buffer is set to drive signals from logic array blocks not between the segmentation buffer and the redundant row to logic array blocks between the segmentation buffer and the redundant row.
A better understanding of the nature and advantages of the present invention may be gained with reference to the following detailed description and the accompanying drawings.